? semiconductor components industries, llc, 2013 october, 2013 ? rev. 1 1 publication order number: dtc115td/d nsbc115td dual npn bias resistor transistors r1 = 100 k , r2 = k npn transistors with monolithic bias resistor network this series of digital transistors is designed to replace a single device and its external resistor bias network. the bias resistor transistor (brt) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base ? emitter resistor. the brt eliminates these individual components by integrating them into a single device. the use of a brt can reduce both system cost and board space. features ? s and nsv prefix for automotive and other applications requiring unique site and control change requirements; aec-q101 qualified and ppap capable ? simplifies circuit design ? reduces board space ? reduces component count ? these devices are pb ? free, halogen free/bfr free and are rohs compliant maximum ratings (t a = 25 c, common for q1 and q2, unless otherwise noted) rating symbol max unit collector ? base voltage v cbo 50 vdc collector ? emitter voltage v ceo 50 vdc collector current ? continuous i c 100 madc input forward voltage v in(fwd) 40 vdc input reverse voltage v in(rev) 6 vdc stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. ordering information device package shipping ? NSBC115TDP6T5G sot ? 963 8,000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. http://onsemi.com marking diagram pin connections (3) (2) (1) q 1 q 2 r 1 r 2 r 1 r 2 (4) (5) (6) af = specific device code m = date code* =pb ? free package (note: microdot may be in either location) *date code orientation may vary depending upon manufacturing location. sot ? 963 case 527ad afm 1
nsbc115td http://onsemi.com 2 thermal characteristics characteristic symbol max unit nsbc115tdp6 (sot ? 963) one junction heated total device dissipation t a = 25 c (note 1) (note 2) derate above 25 c (note 1) (note 2) p d 231 269 1.9 2.2 mw mw/ c thermal resistance, (note 1) junction to ambient (note 2) r ja 540 464 c/w nsbc115tdp6 (sot ? 963) both junction heated (note 3) total device dissipation t a = 25 c (note 1) (note 2) derate above 25 c (note 1) (note 2) p d 339 408 2.7 3.3 mw mw/ c thermal resistance, (note 1) junction to ambient (note 2) r ja 369 306 c/w junction and storage temperature range t j , t stg ? 55 to +150 c 1. fr ? 4 @ 100 mm 2 , 1 oz. copper traces, still air. 2. fr ? 4 @ 500 mm 2 , 1 oz. copper traces, still air. 3. both junction heated values assume total power is sum of two equally powered channels.
nsbc115td http://onsemi.com 3 electrical characteristics (t a = 25 c, common for q 1 and q 2 , unless otherwise noted) characteristic symbol min typ max unit off characteristics collector ? base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector ? emitter cutoff current (v ce = 50 v, i b = 0) i ceo ? ? 500 nadc emitter ? base cutoff current (v eb = 6.0 v, i c = 0) i ebo ? ? 0.1 madc collector ? base breakdown voltage (i c = 10 a, i e = 0) v (br)cbo 50 ? ? vdc collector ? emitter breakdown voltage (note 4) (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc on characteristics dc current gain (note 4) (i c = 5.0 ma, v ce = 10 v) h fe 160 350 ? collector ? emitter saturation voltage (note 4) (i c = 10 ma, i b = 5.0 ma) v ce(sat) ? ? 0.25 vdc input voltage (off) (v ce = 5.0 v, i c = 100 a) v i(off) ? 0.6 ? vdc input voltage (on) (v ce = 0.2 v, i c = 1.0 ma) v i(on) ? 1.0 ? vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.25 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor r1 70 100 130 k resistor ratio r 1 /r 2 ? ? ? 4. pulsed condition: pulse width = 300 msec, duty cycle 2%. figure 1. derating curve ambient temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0 50 100 150 200 250 p d , power dissipation (mw) 150 (1) (1) sot ? 963; 100 mm 2 , 1 oz. copper trace
nsbc115td http://onsemi.com 4 typical characteristics nsbc115tdp6 figure 2. v ce(sat) vs. i c figure 3. dc current gain i c , collector current (ma) i c , collector current (ma) 40 30 20 50 10 0 0.01 0.1 10 100 10 1 10 100 1000 figure 4. output capacitance figure 5. output current vs. input voltage v r , reverse voltage (v) v in , input voltage (v) 50 40 30 20 10 0 0 0.4 0.8 1.2 1.6 2.0 2.4 24 20 28 16 12 8 4 0 0.1 1 10 100 figure 6. input voltage vs. output current i c , collector current (ma) 40 30 50 20 10 0 0.1 1 10 100 v ce(sat) , collector ? emitter voltage (v) h fe , dc current gain c ob , output capacitance (pf) i c , collector current (ma) v in , input voltage (v) i c /i b = 10 150 c ? 55 c 25 c v ce = 10 v 150 c ? 55 c 25 c f = 10 khz i e = 0 a t a = 25 c v o = 5 v 150 c ? 55 c 25 c v o = 0.2 v 150 c ? 55 c 25 c 0.01 1
nsbc115td http://onsemi.com 5 package dimensions sot ? 963 case 527ad issue e dim min nom max millimeters a 0.34 0.37 0.40 b 0.10 0.15 0.20 c 0.07 0.12 0.17 d 0.95 1.00 1.05 e 0.75 0.80 0.85 e 0.35 bsc 0.95 1.00 1.05 h e e d c a h e 123 4 5 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. x y top view side view e b x 0.08 6x y bottom view 6x 0.35 pitch 1.20 0.20 dimensions: millimeters recommended package outline mounting footprint l 0.19 ref l2 0.05 0.10 0.15 l 6x l2 6x 6x 0.35 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 dtc115td/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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